AMD has revealed new technical details about its Zen 6 CPU architecture, including a claimed 27% average improvement in instructions per clock (IPC) over Zen 5 in selected server workloads. The architecture debuts in the company’s sixth-generation EPYC 9006 processors, codenamed Venice, which feature redesigned execution resources, expanded cache configurations and core counts reaching 256.
The disclosures accompanied AMD’s November 10, 2026, announcement of general availability for its latest EPYC server processors. AMD also provided a detailed architectural presentation led by Mike Clark, one of the principal architects behind the Zen processor family, explaining how Zen 6 builds on the changes introduced with Zen 5.
Although Zen 6 is relevant to AMD’s future Ryzen processors, the disclosed 27% IPC improvement comes from enterprise, cloud and AI workloads. It should not be interpreted as a confirmed performance increase for desktop applications or gaming.
AMD’s IPC calculation also uses an unusual comparison. The company measured 16 active Zen 6c cores within a single compute chiplet against 16 Zen 5 cores distributed across two eight-core chiplets, with both configurations operating at the same frequency.
AMD’s figures indicate approximately 20% improvement in conventional workloads and around 31% in AI-focused workloads, producing the reported 27% average. Because the comparison involves different chiplet layouts and shared-cache arrangements, the result does not represent a conventional single-core IPC comparison.
The distinction is particularly important when evaluating potential Ryzen performance. Different cache configurations, memory access patterns and application workloads can affect how architectural improvements translate into actual performance.
Zen 6 introduces substantial changes to the processor’s instruction-handling capabilities. AMD has expanded the operation cache to approximately 6,750 entries and increased its delivery bandwidth from 12 to 18 operations per clock. These improvements extend the dual-pipeline front-end approach introduced with Zen 5, allowing the processor to supply more work to its execution units.
The execution engine has also received larger scheduling structures and additional capacity for handling instructions simultaneously. The reorder buffer increases from 448 entries in Zen 5 to 640 entries in Zen 6, while the physical register resources expand from 240 to 352 entries.
These changes are intended to help the processor manage more instructions in flight, potentially reducing situations where execution units remain underutilized while waiting for other operations to finish.
AMD has also redesigned parts of the integer execution architecture, introducing larger scheduling resources and greater flexibility between arithmetic and address-generation operations. The changes support Zen 6’s wider instruction pipeline and are intended to improve overall throughput.
Vector processing receives additional attention. Zen 6 continues supporting AVX-512 while introducing native FP16 operations and Bit Matrix Multiply instructions. AMD has also improved VNNI-INT8 processing and expanded execution flexibility for 256-bit vector operations.
These features primarily address computational workloads such as scientific processing, AI inference and other applications that benefit from vector instructions. Their contribution to gaming performance will depend on whether individual game engines and software workloads can use the expanded capabilities.
One of the largest architectural changes concerns AMD’s compute chiplets, formally called Core Complex Dies (CCDs).
Standard Zen 6 chiplets now accommodate 12 cores, compared with eight cores in the previous mainstream Zen 5 chiplet design. The density-focused Zen 6c variant scales further, supporting 32 active cores within a single CCD.
AMD has also revised its cache allocation. Standard Zen 6 chiplets feature 48MB of shared L3 cache, while 32-core Zen 6c chiplets provide 128MB.
This gives Zen 6c approximately 4MB of L3 cache per active core, matching the allocation of standard Zen 6 cores. Previous Zen 5c designs offered approximately 2MB per core.
The increased cache allocation is particularly significant for dense server configurations, where many processor cores compete for memory resources. However, the larger total cache capacity disclosed for server chiplets does not establish the cache configuration of future consumer Ryzen processors.
The new architecture also introduces changes to chiplet communication. AMD uses an Elevated Fanout Bridge connection between compute chiplets and the I/O die, designed to improve energy efficiency when transferring data between different parts of the processor.
For Venice, AMD combines these architectural improvements with TSMC’s advanced 2nm manufacturing technology. The server lineup supports configurations containing up to 256 cores, with simultaneous multithreading continuing to provide two threads per core.
The expanded core counts, cache capacity and updated interconnect contribute to AMD’s broader effort to improve processor throughput without relying exclusively on higher clock speeds.
The newly disclosed architecture also provides additional context for the Zen 6c Geekbench performance results, which showed an EPYC 9996 processor outperforming a frequency-matched Ryzen 7 9700X by up to 16.5% in single-core testing. That benchmark and AMD’s newly disclosed IPC figures measure different workloads and should not be treated as directly interchangeable.
For PC enthusiasts, the architectural presentation offers a clearer understanding of the improvements that could eventually influence future Ryzen desktop and laptop processors. Wider instruction delivery, additional execution resources and revised chiplet designs are all relevant developments, but their impact depends on the final consumer implementations.
AMD has not demonstrated that its 27% server IPC improvement applies to gaming, nor does the Venice announcement establish gaming performance figures for upcoming Ryzen CPUs. Consumer-specific benchmarks will be necessary to determine how much of Zen 6’s architectural progress translates into real-world desktop performance.
